Recently, I had to design a circuit real quick that transmitted 4 parallel TTL data bits over 350m of twisted pair cable. I needed to feed in four parallel data bits at one end, and get 4 parallel data bits out the other end, completely transparent to the transmitting and receiving circuits. I decided to implement this using a PIC 16F84 for both an encoder and decoder, and use RS-485 drivers (DS26C31 and DS26C32) to drive the 350m cable. I only needed five I/O pins per PIC, so this could have been implemented using the smaller 8pin 12C508 device, but the 16F84 has the advantage of being reprogrammable, and PCB size or cost wasn't an issue anyway. The design presented here can be easily modified for any number of bits and any desired interface RS-232, Fiber optic, almost anything. In fact, the software is interfacing independent, you only need to change the interface chips. This is the diagram figure;
As you can see, there isn't much too it. I have omitted the power pins and XTAL inputs which are also used. The MCLR line must also be tied HIGH on both chips. Port A is not used The software is written for an external crystal running at 1MHz, although the actual speed isn't important, but you must have both the encoder and decoder at the same speed. The watchdog has been enabled. There is a burst of five bits every 100ms. The start bit is 0.5ms, and the data bits are 1ms each. This is assuming a 1MHz crystal clock is used. This gives an update rate of 10Hz, which may not seem very fast, but was more than sufficient for driving the relays in my application. The timing could be easily changed in software. The decoder simply waits in a loop for the start bit, and then times for 1ms before sampling the first data bit. This sample then occurs exactly in the centre of the data bit to ensure a reliable reading. The subsequent data bits are then read every 1ms as well. The timing diagram figure;
As you can see, there isn't much too it. I have omitted the power pins and XTAL inputs which are also used. The MCLR line must also be tied HIGH on both chips. Port A is not used The software is written for an external crystal running at 1MHz, although the actual speed isn't important, but you must have both the encoder and decoder at the same speed. The watchdog has been enabled. There is a burst of five bits every 100ms. The start bit is 0.5ms, and the data bits are 1ms each. This is assuming a 1MHz crystal clock is used. This gives an update rate of 10Hz, which may not seem very fast, but was more than sufficient for driving the relays in my application. The timing could be easily changed in software. The decoder simply waits in a loop for the start bit, and then times for 1ms before sampling the first data bit. This sample then occurs exactly in the centre of the data bit to ensure a reliable reading. The subsequent data bits are then read every 1ms as well. The timing diagram figure;
